In recent years, a system-in-package technology has been an object of public attention. Such a system-in-package technology provides a shorter period of time for fabricating a high performance system, in which a plurality of semiconductor chips, containing a semiconductor integrated circuit, is mounted in a package at a high density. It has been demanded that a system-in-package contains a plurality of semiconductor chips mounted in a three dimension manner to miniaturize the size significantly. In order to respond to such a demand, an advanced semiconductor package has been introduced, in which a plurality of semiconductor chips are mounted on a special purpose semiconductor chip, called “semiconductor interposer”. Such a semiconductor interposer includes through electrodes therein.
According to a conventional package structure using semiconductor interposers, electrical circuits formed in semiconductor chips may have malfunction due to an undesired light comes into the semiconductor chips. Such a problem of malfunction is remarkable to memory chips, which include charge-storage layers being influenced easily by lights.
In order to prevent such a problem, Japanese Patent Publication No. 2005-44861A (Patent Related Publication 1) proposed an invention, in which a three-dimensionally mounted substrate includes a shield layer made of metal to shield undesired lights except light signals to be come into integrated circuits.
[Patent Related Publication 1] JP Publication No. 2005-44861A
However, according to the invention described in the Patent Related Publication 1, it is difficult to shield lights come from a side of the semiconductor package in a horizontal direction. When a plurality of semiconductor chips are layered or piled up, a thickness of the semiconductor package is increased. As a result, lights would come more easily in horizontal directions into the semiconductor package as compared to a semiconductor package containing a single semiconductor chip.